Solid-state imaging device, method for driving dolid-state imaging device, imaging method, and imager

ABSTRACT

The present invention relates to a CCD solid state image sensor of a scanning read-out type and to a drive method thereof as well as an image pick-up method and the image pick-up device, particularly in which a plurality of vertical CCD columns can be assigned to one electric-charge detection unit with the small number of wiring. In the present invention, adjacent columns of the vertical CCDs are assigned to one electric-charge detection unit. Further, the stages of the voltage transfer between the vertical CCD column and a voltage detection unit is made different; the electrode arrangement is devised; or the drive timing is adjusted. Accordingly, the phase of electric-charge transfer with respect to the plurality of adjacent vertical CCD columns, when the horizontal electric-charge at the same position in the direction of the row obtained by the photo-conductive units is made to reach the electric-charge detection unit, becomes different.

TECHNICAL FIELD

The present invention relates to a solid state image sensor, a drivemethod of the solid state image sensor, an image pick-up method and animage pick-up device.

BACKGROUND ART

Conventionally, CCD (charge couple device) has widely been used as anelectric-charge transfer unit of an image pick-up device. When the CCDis used for an image pick-up device, approximately the same number ofvertical CCDs as the number of horizontal pixels and one horizontal CCDare arranged, and electric-charge is transferred from the photo-electricconverter that is arranged in each pixel to the vertical CCD, thehorizontal CCD and the output unit.

Lately, due to the demand for the miniaturization and the highresolution of an image in a camcorder and others, increasing the numberof pixels in the same optical size is attempted so that the pictureresolution of an image pick-up device is improved. However, the read-outtime unavoidably increases when the number of pixels is increased. Onthe contrary, when all the pixels are read out during the same period oftime, the clock frequency for the read-out necessarily rises, becausethe number of signals which must be read out in the same period of timeincreases.

FIG. 17 shows a conventional CCD solid state image sensor. A CCD solidstate image sensor 1 shown in FIG. 17 is of an inter-line method, and anumber of photo-diodes (photo-conductive units) 4 each corresponding toa pixel 3 are arranged in an image pick-up area 2 in a two-dimensionalmatrix shape in the vertical (column) direction and in the horizontal(row) direction. Further, in the image pick-up area 2, a plurality ofvertical CCDs 5 are provided for respective columns of the photo-diodes4, which vertically transfer the signal electric-charge e read out fromeach photo-diode 4 through a read-out gate 8.

Furthermore, a horizontal CCD 6 which extends in the right-leftdirection on the drawing is provided as one line close to each endportion in the transfer direction of the plurality of columns ofvertical CCDs 5, that is, close to the last row thereof. Anelectric-charge detection unit 7 composed of for example afloating-diffusion amplifier FDA is provided in the end portion in thetransfer direction of the horizontal CCD 6 (on the left side of thedrawing). The electric-charge detection unit 7 converts a signalelectric-charge input in order from the horizontal CCD 6 into a pixelsignal voltage to be output. An image signal S is obtained by outputtingthe pixel signal voltage in time series.

FIG. 18 is a schematic view of a timing chart of a transfer pulse whichdrives the conventional solid state image sensor 1. The signalelectric-charge obtained by the photo-electric conversion in thephoto-diode 4 corresponding to the pixel 3 in the image pick-up area 2is read out to the vertical CCD 5 through the read-out gate 8. Driven byfor example the vertical transfer pulses φV1 to φV4 used for thefour-phase drive, the vertical CCD 5 transfers the signalelectric-charge e that is read out to the vertical CCD 5 to thehorizontal CCD 6 with a plurality of rows in parallel. The horizontalCCD 6 is driven by the horizontal transfer pulses φH1 and φH2 used fortwo-phase drive and further transfers the signal electric-charge etransferred from the vertical CCD 5 to the electric-charge detectionunit 7. Thus, the signal electric-charge e is converted into the imagesignal S in time series and is output from the electric-charge detectionunit 7.

At this time, as shown in FIG. 18, when a period of time that the signalelectric-charge e obtained in the photo-diode 4 is transferred to thehorizontal CCD 6 through the vertical CCD 5 and a period of time thatthe signal electric-charge e transferred to the horizontal CCD 6 istransferred to the electric-charge detection unit 7 through thehorizontal CCD 6 are compared, the latter is overwhelmingly longer.Specifically, the time required to read out the signal electric-charge eof all the pixels 3 is limited by the transfer speed of the horizontalCCD 6. That is, the clock frequency of the horizontal CCD 6 is thehighest in the solid state imaging device, and the restriction thereofbecomes one of the key points for obtaining the high density pixels.

Further, an increase in the number of pixels in the same optical sizecauses a problem that the area of the sensor portion per one pixeldecreases, consequently which causes a problem of the decline ofsensitivity.

A limit on this clock frequency and the sensitivity decline per onepixel are the limitation factors for the increase of the pixel numbersin the CCD solid state image sensor which is the mainstream of the solidstate image sensor of late. This fact is explained specifically in thefollowings.

As a read-out method in which the clock frequency of the horizontal CCDis reduced, mainly two kinds of method have been devised. The firstmethod is a method proposed in the Japanese Patent No. 2785782 andJapanese Published Patent Application 2001-119010 for examples, in whichthe sensor portion of the solid state image sensor is divided into aplurality of blocks and electric-charge is transferred by the horizontalCCD of each block. Hereinafter, the first method is called a “pluralityof horizontal CCDs read-out method”.

The second method is a method proposed in Japanese Published PatentApplication H6-97414 and Japanese Patent No. 3057898 for examples, inwhich an electric-charge detection unit such as a floating-diffusionamplifier FDA or the like is provided for each vertical CCD, a signalelectric-charge is converted into a voltage signal in thiselectric-charge detection unit, and the voltage signal of each verticalCCD is sequentially output to an output unit by the switch selection.Hereinafter, the second method is called a “scanning read-out method”.

Hereupon, further consideration is given to the above-mentioned tworead-out methods. Considering the “plurality of horizontal CCDs read-outmethod” first, the horizontal CCD is divided into the plurality ofblocks, and the data rate apparently improves by outputting theplurality of outputs in parallel. Accordingly, the clock frequency ofthe horizontal CCD can be reduced.

However, since the electric-charge detection unit in which a signalelectric-charge is converted into the pixel signal is divided into aplurality of portions, the density unevenness occurs in the signal levelwhich is output by each block and the seam portion between the blocksbecomes discontinuous due to the difference of the conversion gain inthe divided electric-charge detection units. Since the whole of thepicture is divided into the plurality of blocks, this density unevennessappears on the image as a thick stripe pattern and the stripe pattern(density unevenness) can be visible because of comparatively lowfrequency.

Further, basically the read-out method remains unchanged from aconventional CCD type image sensor, and a serial output is performedwith respect to one block. In the future, in order to compensate for thedecline in sensitivity caused by the high density pixels, the signalcompensation with an adding method in which the signal of the same colorin the same line (row) is mixed with each other is considered to beimportant; however, the selectivity of the image signal of the“plurality of horizontal CCDs read-out method” is extremely small,because basically the method is of the serial output. Therefore, thedecline in sensitivity caused by the high density pixels may not becompensated with signal correction.

Next, when considering the “scanning read-out method”, as indicated inJapanese Published Patent Application H6-97414, an electric-chargedetection unit such as a floating-diffusion amplifier FDA is providedcorresponding to each column CCD or to plurality of column CCDs. In thiscase, the density unevenness in the electric-charge detection unitcaused by the difference in the conversion gain becomes invisible on thepicture due to comparatively high frequency, which is not a problem;however, the reset dispersion among the electric-charge detection unitsbecomes a problem. In order to eliminate the reset dispersion, it isdesirable to provide a CDS (Correlated Double Sampling) circuitsubsequent to the electric-charge detection unit, for example.Considering the size of the CDS circuit (most part of the CDS circuitarea is the capacity of several pF), a method in which the number of CDScircuits can be reduced is desirable.

In this case, a first method in which an output signal from theelectric-detection unit provided in each column CCD is input to one CDScircuit by a switch selection, and a second method in which oneelectric-charge detection unit is provided corresponding to a pluralityof column CCDs and one CDS circuit is provided with each electric-chargedetection unit are considered.

However, though the number of CDS circuits decreases in the firstmethod, the processing frequency in the CDS circuit portion is equal tothe clock frequency of the horizontal CCD, which becomes a problem withrespect to the high density pixels. In other words, the problem of thehigh clock frequency is only passed on to the CDS circuit from thehorizontal CCD. In view of the above, the second method in which oneelectric-charge detection unit is provided corresponding to a pluralityof column CCDs is more desirable.

However, in the second method, a selective gate VOG (read-out gate)which selects the plurality of column CCDs for reading out the signalelectric-charge must be provided between the vertical CCD and theelectric-charge detection unit. Providing the selective gate between thevertical CCD and the electric-charge detection unit is possible whenconsidering the “scanning read-out method” about an equivalent circuitas shown in FIG. 19A; however, wiring of a selection wire to theread-out gate becomes a problem when the actual pattern is considered.

Specifically, as shown in FIG. 19B, when four columns CCD 11 is assignedto one electric-charge detection unit 12, the outside columns A and Dcan be patterned with the selection wire led to the selective gates 13Aand 13D; however, there is no space for the inside columns B and C whichexist in the center, and it is difficult to form as an actual patternthe selection wire led to the selective gates 13B and 13C shown with aslant lines. Patterning may be considered to perform on thefloating-diffusion FD; however, a problem of noise occurrence is newlycaused.

As described above, a problem of sensitivity decline and the decrease inthe clock frequency of the horizontal CCD caused by increasing the pixeldensity remains unsolved in the conventional CCD solid state imagesensor.

DISCLOSURE OF THE INVENTION

The present invention aims to provide a CCD solid state image sensor inwhich both the clock frequency and the sensitivity can be improved, amethod for driving the CCD solid state image sensor, and an imagepick-up method and an image pick-up device which use the CCD solid stateimage sensor.

A first solid state image sensor according to the present inventionincludes: a plurality of photo-conductive units which are arranged ineach direction of the row and the column in the two-dimensional shapeand which obtain a signal electric-charge by receiving light, a columnelectric-charge transfer unit which transfers a signal electric-chargeobtained by the photo-conductive unit in the column direction, anelectric-charge detection unit which is provided for every plurality ofadjacent columns and which converts the signal electric-chargetransferred from the column electric-charge transfer unit into a pixelsignal, and a dummy electric-charge transfer unit arranged between thecolumn electric-charge transfer unit and the electric-charge detectionunit, in which the number of stages of the electric-charge transfer ismade different with respect to each of the plurality of columns.

In the above first solid state image sensor, it is desirable that anelectrode for the vertical transfer drive is shared with the pluralityof adjacent column electric-charge transfer units.

Further, the electric-charge detection unit can be provided for everytwo adjacent columns. In this case, the dummy electric-charge transferunit makes the phase of the electric-charge transfer, when the signalelectric-charge of the photo-conductive unit in the same row directionreaches the electric-charge detection unit, different by 180 degreesinverted in the number of stages of electric-charge transfer.

A second solid state image sensor according to the present inventionincludes a plurality of photo-conductive units which are arranged ineach direction of the row and the column in the two-dimensional shapeand which obtain a signal electric-charge by receiving light, a columnelectric-charge transfer unit which transfers a signal electric-chargeobtained by the photo-conductive unit in the column direction, and anelectric-charge detection unit provided in every plurality of adjacentcolumns and which converts the signal electric-charge transferred by thecolumn electric-charge transfer unit into a pixel signal. Further, anelectrode used for a vertical transfer drive is formed such that in thecase where a common vertical transfer control signal is applied to theplurality of adjacent columns, phases of electric-charge transfer whenthe signal electric-charge at the same position in the row directionobtained in the photo-conductive units reaches the electric-chargedetection unit are made different.

In the first or the second solid state image sensor according to thepresent invention, the electric-charge detection unit is preferablyprovided with a floating diffusion (floating diffusion layer) on theinput side of the signal electric-charge. Further in this case, it isdesirable to have a read-out gate on the input side, which is sharedwith the plurality of adjacent columns to read out the signalelectric-charge. Further, a wiring to the read-out gate may be sharedwith a wiring to the read-out gate for the other adjacentelectric-charge detection units.

Thus, the above-mentioned first and second solid state image sensors maybe required to be formed including a plurality of photo-conductiveunits, a column electric-charge transfer unit which transfers the signalelectric-charge obtained by the photo-conductive unit in the columndirection and a electric-charge detection unit which is provided foreach column and which converts the signal electric-charge transferred bythe column electric-charge transfer unit into the pixel signal; in whichwhen the common vertical transfer control signal is applied to theplurality of adjacent columns, the phases of the electric-chargetransfer are different when the signal electric-charge at the sameposition in the row direction obtained by the photo-conductive unitsreaches the electric-charge detection unit.

Then, as a specific means to realize the above, the first solid stateimage sensor uses a dummy electric-charge transfer unit in which thenumber of stages of the electric-charge transfer is different, and thesecond solid state image sensor uses the configuration in which theformation of the vertical transfer electrode to which the verticaltransfer control signal (transfer pulse) is applied is correspondinglymade.

A third solid state image sensor according to the present invention,which is obtained with the different viewpoint from the above-mentionedfirst and second solid state image sensors, includes: a plurality ofphoto-conductive units which are arranged in each direction of the rowand the column in the two-dimensional shape and which obtain a signalelectric-charge by receiving light, a column electric-charge transferunit which transfers the signal electric-charge obtained by thephoto-conductive unit in the column direction, and a electric-chargedetection unit which is provided in every two adjacent columns and whichconverts the signal electric-charge transferred by the columnelectric-charge transfer unit into a pixel signal. Further, a selectivegate is provided independently on the input side of the electric-chargeof the electric-charge detection unit for each of the two adjacentcolumns to read out the signal electric-charge.

In the first, second and third solid state image sensors according tothe present invention, each electric-charge detection unit may include areset gate in the electric-charge detection unit to be initialized afterconverting the signal electric-charge into the pixel signal.

Alternatively, it is desirable that a differential detection unit whichdetects the difference between the output without the signalelectric-charge and the signal level with the signal electric-charge inthe pixel signal is provided subsequently to the electric-chargedetection unit.

Further, it is desirable to provide a plurality of electric-chargedetection units for the plurality of adjacent columns in the columndirection with a plurality of adjacent columns as a group and to providea horizontal scanning unit subsequent to the plurality ofelectric-charge detection units, which selects and outputs the pixelsignals output from each of the plurality of electric-charge detectionunits sequentially in time series in the row direction.

A drive method of the solid state image sensor according to the presentinvention is the drive method which drives the first, second or thirdsolid state image sensor according to the present invention, in whichpixel signals with respect to a plurality of adjacent columns are eachdriven to be output with a different phase in the transfer of the signalelectric-charge in the column direction.

Further, for example, in the case where the electric-charge detectionunit includes a selective gate to read out the signal electric-chargeand a reset gate to be initialized after converting the signalelectric-charge into the pixel signal, when the selective gate is off,the reset gate is turned on, so that the plurality of adjacent columnscan be read out sequentially.

An image pick-up method according to the present invention is the imagepick-up method, in which an image signal is obtained using the first,second or third solid state image sensor, and first, the pixel signalswith respect to the plurality of adjacent columns are obtained withdifferent phases in the transfer of the signal electric-charges in thecolumn direction. Next, the image signal with respect to each differentphase is obtained by selecting the obtained pixel signals sequentiallyin time series in the row direction. Finally, the image signalsequentially aligned in the row direction is obtained by rearranging thepixel signals of the image signal in the row direction in accordancewith the order of the plurality of columns.

An image pick-up device according to the present invention is the imagepick-up device which obtains an image signal using the first, second orthird solid state image sensor, and includes a horizontal scanning unitwhich obtains an image signal with respect to each of the differentphases by sequentially selecting the pixel signals, which is output fromthe solid state image sensor with a different phase in the transfer ofthe signal electric-charges in the column direction, in time series inthe row direction, and a row adjustment unit which obtains the imagesignal sequentially aligned in the row direction by rearranging thepixel signals of the image signal that is output from the horizontalscanning unit in the row direction in accordance with the order of theplurality of columns.

With respect to the first solid state image sensor, one electric-chargedetection unit is assigned to a plurality of columns, and a dummyelectric-charge transfer unit is provided between the columnelectric-charge transfer unit and the electric-charge detection unit.Accordingly, various electrodes and gates such as a vertical transferelectrode and an electrode used for the selective gate can be sharedwith the plurality of columns.

With respect to the second solid state image sensor, one electric-chargedetection unit is assigned to a plurality of columns, and an electrodeused for a vertical transfer drive is formed such that phases ofelectric-charge transfer, when the signal electric-charge of thephoto-conductive units in the same row reaches the electric-chargedetection unit, are different with respect to the plurality of adjacentcolumn electric-charge transfer units. Accordingly, various electrodesand gates such as a vertical transfer electrode and an electrode usedfor the selective gate can be shared with respect to the plurality ofcolumns.

With respect to the third solid state image sensor, one electric-chargedetection unit is assigned to every two columns, and a selective gate toread out a signal-charge is provided independently on the input side ofthe signal electric-charge in the electric-charge detection unit foreach of the two columns. Accordingly, the problem of wiring of theselective wire to the selective gate is resolved.

In the drive method according to the present invention, the pixelsignals with respect to a plurality of adjacent columns are driven to beoutput with different phases in the vertical transfers. Further,according to the image pick-up method and image pick-up device of thepresent invention, the image signal is obtained with respect to eachphase by sequentially selecting in the row direction in time series thepixel signals obtained with the different phases in the verticaltransfers. Then, image picture information on the image pick-up area andthe image signals are made to have the same arrangement by rearrangingthe pixel signals in the row direction in accordance with the order ofalignment of vertical columns.

As described above, the solid state image sensor (the first and secondsolid state image sensors, for example) according to the firstembodiment of the present invention was formed such that the phases ofthe electric-charge transfers when the signal electric-charges at thesame position in the direction of the row obtained by thephoto-conductive units reach the electric-charge detection unit are madedifferent, after assigning the plurality of adjacent columns to oneelectric-charge detection unit, making the number of stages of thevertical transfer to the electric-charge detection unit becomedifferent, devising an arrangement of the electrode, adjusting the drivepulse timing or performing other operations. Accordingly, a selectivegate VOG is not required to be provided independently with respect to aplurality of columns, and the restriction in wiring decreases greatly,and a space for such as a CDS circuit of the subsequent stage can besecured.

Furthermore, in the solid state image sensor (the third solid stateimage sensor, for example) according to the second embodiment of thepresent invention, that is, in the configuration in which the twocolumns are assigned to one electric-charge detection unit and aselection mechanism (the selective gate) which controls theelectric-charge transfer from the columns is provided independently,though the number of wiring to the selective gate is larger than thefirst embodiment, the wiring space for the selective gate in the centerportion does not become a problem.

As described above, in the solid state image sensor of the presentinvention, since signals in the horizontal direction are obtained byusing the common vertical transfer electrode for respective columns andby using the common selective gate for the plurality of columns toreduce the restriction in the wiring and to sequentially select andrearrange in the horizontal direction the pixel signals of each columnwhich are converted in the electric-charge detection unit, the imagesignal corresponding to the signal electric-charge can be obtainedwithout employing the electric-charge transfer unit in the horizontaldirection (such as a horizontal CCD).

Since the electric-charge transfer unit used in the horizontal directionis not employed, the problem that the horizontal clock frequency becomesa limit when the number of pixels of a solid state image sensorincreases can be resolved.

Since a signal can be read by each column, the sensitivity decline perone pixel caused by the high density pixels can be compensated using asignal of adjacent pixels (or, the same color pixel which is positionedby two pixels apart).

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic constitutional view showing a first embodiment ofan image pick-up device which uses a CCD solid state image sensoraccording to the present invention;

FIG. 2 is a schematic plan view showing the vicinity of the boundaryportion between the vertical CCD and the read-out processing unitaccording to the CCD solid state image sensor of the first embodiment ofthe present invention;

FIG. 3 is a sectional view schematically showing the vicinity of theboundary portion between the vertical CCD and the read-out processingunit according to the CCD solid state image sensor of the firstembodiment of the present invention;

FIG. 4 is a schematic view of a timing chart of vertical transfer pulsesφV1 to φV6 which drive the vertical CCD and the dummy vertical CCD,according to the CCD solid state image sensor of the first embodiment ofthe present invention;

FIG. 5 is a diagram which explains the relationship between the verticaltransfer electrode constituting the vertical CCD and the dummy verticalCCD, and the vertical transfer pulses φV1 to φV6 which are appliedthereto according to the CCD solid state image sensor of the firstembodiment of the present invention;

FIG. 6 is a diagram which explains the relationship between the verticaltransfer pulses φV1 to φV6 which drive the vertical CCD and the dummyvertical CCD, and the electric-charge transfer according to the CCDsolid state image sensor of the first embodiment of the presentinvention;

FIG. 7 is a schematic view of a timing chart of the vertical transferpulses φV1 to φV6, which explains an example of making theelectric-charge transfer into a reverse phase by changing thearrangement of the vertical transfer electrode;

FIG. 8A is a diagram which shows the relationship between the verticaltransfer electrode and the vertical transfer pulses φV1 to φV6 appliedthereto to explain an example of making the electric-charge transferinto a reverse phase by changing an arrangement of the vertical transferelectrode; and FIG. 8B is a schematic view of the patterning on thevertical transfer electrode;

FIG. 9 is a diagram which explains the relationship between the verticaltransfer pulse and the electric-charge transfer;

FIG. 10A is a circuit diagram showing a first example of the structurefor one unit in a read-out processing unit; and FIG. 10B is a diagramshowing each signal waveform;

FIG. 11 is a circuit diagram showing a second example of the structurefor one unit in the read-out processing unit;

FIG. 12A is a block diagram showing an example of the wholeconfiguration of an image pick-up device including a signal processingcircuit connected to the stage subsequent to the read-out processingunit; and FIG. 12B is a block diagram showing the relevant part thereof;

FIG. 13 is a diagram which explains a first modified example of the CCDsolid state image sensor according to the first embodiment of thepresent invention;

FIG. 14 is a diagram which explains a second modified example of the CCDsolid state image sensor according to the first embodiment of thepresent invention;

FIG. 15 is a diagram which explains a modified example when the firstembodiment of the CCD solid state image sensor is driven by four-phasedrive;

FIG. 16A is a circuit diagram of the relevant part which explains theCCD solid state image sensor of the third embodiment of the presentinvention; and FIG. 16B is a schematic plan view thereof;

FIG. 17 is a constitutional diagram showing a conventional CCD solidstate image sensor;

FIG. 18 is a schematic view of a timing chart of the transfer pulsewhich drives the conventional CCD solid state image sensor; and

FIG. 19A is a circuit diagram of the relevant part which explains aproblem of “the scanning read-out method” of the conventional type; andFIG. 19B is a schematic plan view thereof.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be explained indetail with reference to the drawings.

FIG. 1 is a schematic constitutional view showing a first embodiment ofan image pick-up device which uses a CCD solid state image sensoraccording to the present invention and showing the case in which thepresent invention is applied to a CCD area sensor of an inter-linetransfer method.

As shown in FIG. 1, an image pick-up device 20 includes a CCD solidstate image sensor 40 having an image pick-up area 100 and a read-outprocessing unit 200 arranged on the lower side in the drawing withrespect to the image pick-up area 100, and an outside circuit 30 whichdrives the CCD solid state image sensor 10.

The outside circuit 30 includes a drive power source 70 which suppliesto the CCD solid state image sensor 40 a desired drive voltage such as adrain voltage V_(DD), a gate voltage V_(GG) or a reset-drain voltageV_(RD), and a timing generator 80 (TG) which generates various pulsesignals such as the vertical transfer pulses φV1 to φV6, a read-outpulse X_(SG), a selective gate voltage (a fixed voltage) V_(OG), a resetgate pulse φRG, a clump pulse CLP, a hold pulse HP and others whichdrive the CCD solid state image sensor 40, or a control signal CNT andothers with respect to a column selection pulse generator 280.

The CCD solid state image sensor 40 which constitutes the image pick-updevice 20 is formed such that a number of photo-conductive units (sensorunits; photo cells) 120 composed of a PN junction photo diode as anexample of a sensor corresponding to a pixel (unit cell) are arranged onthe semiconductor substrate in the vertical (column) direction and inthe horizontal (row) direction in the two-dimensional matrix shape.Those photo-conductive units 120 convert the incident light entered fromthe light receiving surface into the signal electric-charge inaccordance with the amount of light to be stored.

Further, in the CCD solid state image sensor 40 a vertical CCD 130 whichis an example of the column electric-charge transfer unit having aplurality of vertical transfer electrodes V1 to V6 (six per unit sell inthis embodiment) corresponding to the six-phase drive in each column ofthe photo-conductive unit 120 is provided. The vertical transferelectrodes V1 to V6 almost extend straight in the row direction on thedrawing with respect to the adjacent vertical CCDs 130 in the imagepick-up area 100 so that the signal electric-charges of thephoto-conductive units 120 in the same row are transferred with the samephase to the electric-charge detection unit 210.

The image pick-up area 100 includes a number of photo-conductive units120 arranged in the two-dimensional matrix shape, and a plurality ofvertical CCDs 130 which are provided for each column of thosephoto-conductive unit 120 and which vertically transfer the signalelectric-charge read out from each photo-conductive unit 120 through theread-out gate (not shown in the drawing).

Each of the vertical transfer electrodes V1 to V6 sets a repetition unitin a transfer direction in every one pixel (in other words, unit cell)of the photo-conductive unit 120. The transfer direction is a verticaldirection in the drawing, and the vertical CCDs 130 are provided in thisdirection. Further, a read-out gate portion (transfer gate) ROG existsbetween those vertical CCDs 130 and respective photo-conductive units120. Furthermore, a channel stop (element isolation layer) CS isprovided in the boundary portion of each unit cell. Further, theread-out processing unit 200 is provided close to each end portion inthe transfer direction of the vertical CCDs 130 of the plurality ofcolumns, namely close to the last row of the vertical CCDs 130.

The read-out pulse X_(SG) sent from the timing generator 80 constitutingthe outside circuit 30 is applied to a gate terminal electrode of theread-out gate unit ROG, so that a electric potential under that gateterminal electrode becomes deep and the signal electric-charge stored ineach of the photo-conductive units 120 is read out to the vertical CCD130 through the relevant read-out gate unit ROG. The signalelectric-charge read out to the vertical CCD 130 is sequentiallytransferred to the read-out processing unit 200 along the column withthe vertical transfer pulses φV1 to φV6 of the fixed timing beingapplied to the vertical transfer electrodes V1 to V6 (called sixelectrodes/six-phase drive).

The read-out processing unit 200 includes an electric-charge detectionunit 210 which receives and converts signal electric-charge which isinput sequentially from the vertical CCD 130 into a voltage signal, aband-limit unit 230 which restricts the frequency bandwidth of thevoltage signal converted by the electric-charge detection unit 210, aCDS processing unit 250 which suppresses the reset noise occurred at theelectric-charge detection unit 210, and a column selection unit 270which selects the column of the voltage signal output from the CDSprocessing unit 250 to be output. Further, the read-out processing unit200 includes a column selection pulse generator 280 which generates acolumn selection pulse (horizontal scanning pulse) SP(n) which definesthe scanning in the horizontal direction and supplies the result to acolumn selection unit 270.

Hereupon, this first embodiment is characterized in that theelectric-charge detection unit 210, the band-limit unit 230, the CDSprocessing unit 250 and the column selection unit 270 are provided forevery two adjacent columns. In other words, with respect to one set oftwo adjacent columns in the horizontal direction, the electric-chargedetection unit 210 and others are correspondingly provided respectivelyin the image pick-up area 100 where a plurality of pixel lines includinga photo-conductive unit 120 column composed of a plurality of photodiodes and a vertical CCD 130 connected to each photo-conductive unit120 through each read-out gate unit ROG are arranged in parallel. Thoughan example in which two columns are made to one set is here used, it isnot specially restricted to this value as described in the otherembodiments later on.

In the read-out processing unit 200, the electric-charge detection unit210 stores the signal electric-charge, which is sequentially input fromthe vertical CCD 130 in the image pick-up area 100, in the floatingdiffusion that is not shown, and the signal electric-charge which isconverted into the voltage signal under the controls of the selectivegate voltage V_(OG) and that of the reset gate pulse φRG supplied fromthe timing generator 80 is output as the pixel signal (CCD outputsignal) through the output circuit of, for example, the source-followertype that is not shown.

After converted into the voltage signal by the electric-charge detectionunit 210, the frequency bandwidth of the pixel signal is restricted bythe band-limit unit 230, and then, the reset noise occurred in theelectric-charge detection unit 210 is suppressed by the CDS processingunit 250. The column selection unit 270 outputs the voltage signal fromthe CDS processing unit 250 to the output signal wire 290, when thecolumn selection pulse SP(n) supplied from the column selection pulsegenerator 280 is in active.

In other words, the voltage signal with respect to each of the oddcolumn and even column in the vertical direction is sequentiallyselected by the column selection unit 270 in the horizontal directionand is read out respectively regarding each of the odd column and theeven column (by the time sharing), so that the image signal with respectto each of the odd column and the even column having a different phaseis obtained. Namely, the horizontal scanning unit according to thepresent invention is composed of the picture reproduction means 270 andthe column selection pulse generator 280.

FIGS. 2 and 3 are drawings which show the vicinity of the boundaryportion between the vertical CCD 130 and the read-out processing unit200 in the CCD solid state image sensor 40 of the first embodiment. FIG.2 is a schematic plan view and FIG. 3 is a schematicvertically-sectional view in the direction of the column.

As shown in the drawings, an amplifier FDA of the floating diffusiontype is provided on the side of the vertical CCD 130 which is the stageprior to the electric-charge detection unit 210. In other words, theamplifier FDA includes a selective gate VOG, a floating diffusion FDwhich is the N+ region, a reset gate wire RG, a reset drain RD which isthe N+ region and others. One electric-charge detection unit 210 isrespectively provided corresponding to two adjacent columns of the oddcolumns A, C, E . . . and the even columns B, D, F . . . of the verticalCCDs 130.

A plurality of vertical transfer electrodes (six vertical transferelectrodes V1 to V6 per one pixel in this embodiment) are formed abovethe vertical CCD 130, and a channel stop CS is formed between respectivecolumns, in which the photo-conductive unit 120 not shown and theread-out gate unit ROG are provided.

A dummy vertical CCD 132 which is an example of the dummyelectric-charge transfer unit is provided between the selective gate VOGside of the electric-charge detection unit 210 and the vertical CCD 130in the image pick-up area 100. The dummy vertical CCD 132 is coveredwith a shade coating. With respect to the length of the dummy verticalCCD 132, namely with respect to the number of stages of the dummyvertical transfer electrode, the odd column has three stagescorresponding to the transfer electrodes V1 to V3, and the even columnhas six stages of V1 to V6. In other words, the length of the verticalCCD including the whole of the vertical CCD 130 and the dummy verticalCCD 132 (the number of stages of the registers corresponding to theelectrodes) is different only by three stages for the register.

The vertical transfer pulses φV1 to φV6 each having a timing describedlater on are sequentially applied to the transfer electrodes V1 to V6 ofthe vertical CCD 130 and to the transfer electrodes V1 to V6 of thedummy vertical CCD 132 in common.

With respect to the length of the dummy vertical CCD 132, namely withrespect to the number of stages of the dummy vertical transferelectrode, three stages of V1 to V3 are provided for the odd column, andsix stages of V1 to V6 are provided for the even column. Thus, even ifthe same vertical transfer pulses 100 V1 to φV6 are applied to both theodd columns and even columns, the transfer phase (read-out phase) of thesignal electric-charge from the vertical CCD 130 to the electric-chargedetection unit 210 is shifted by 180 degrees, and the electric-chargereaches the electric-charge detection unit 210 (the floating diffusionFD in this embodiment) at different timing.

In other words, the length of the dummy vertical CCD 132 (the number ofstages of the electric-charge well) connected to the floating diffusionFD is changed, and by shifting the electric-charge transfer phase by 180degrees between the vertical CCDs 130 of two columns when reaching thefloating diffusion FD, the signal electric-charge of the vertical CCDs130 of two columns can be transferred to one floating diffusion FD witha single selective gate VOG to the floating diffusion FD, instead ofusing two selective gates VOG for each vertical CCD for selecting thevertical CCD 130. As a result, the number of wiring connected to thegate can be reduced in comparison with “the scanning read-out method” ofthe conventional type and the sensor area can be used efficiently.

Note that the number of stages of the dummy vertical CCD 132 is notlimited to that of the example shown in the drawing and can be changedappropriately such that the signal electric-charge of each column ismade to reach the electric-charge detection unit 210 (the floatingdiffusion FD in this embodiment) with different phase (timing) in onecycle of the transfer in accordance with: the number of phases, thenumber of the transfer electrodes, the number of columns for oneelectric-charge detection unit 210 and others. Further, in the exampleshown in the drawing, the relation of “Db=Da+3” is only required betweenthe number of stages Da of the odd column and the number of stages Db ofthe even column such as 0 stage for odd column and three stages for evencolumn, removing the common portion of V1 to V3 with respect to the oddcolumn and the even column, for example. Further, the relation betweenthe odd column and the even column can be reversed such as “Da=Db+3”.

FIGS. 4 to 6 are drawings explaining the relationship between thevertical transfer pulses φV1 to φV6 which drive the vertical CCD 130 andthe dummy vertical CCD 132 and the electric-charge transfer in the CCDsolid state image sensor 40 of the first embodiment. Hereupon, FIG. 4 isa basic-type timing chart of the vertical transfer pulses φV1 to φV6 ofthe six-phase drive. FIG. 5 is a schematic view showing the relationshipbetween the transfer electrodes V1 to V6 of the odd column and evencolumn in the vertical CCD 130 and in the dummy vertical CCD 132 and thevertical transfer pulses φV1 to φV6 applied thereto. Further, FIG. 6 isa schematic view showing the relationship between a voltage potential inthe vertical CCD 130 and in the dummy vertical CCD 132 shown in FIG. 5and the electric-charge transfer.

As described above, the register (electric-charge well; charge packet)corresponding to respective transfer electrodes V1 to V6 of the verticalCCD 130 and the dummy vertical CCD 132 is driven by the verticaltransfer pulses φV1 to φV6 shown in FIG. 4 in common.

As shown in FIG. 5, in the electrode structure in which six transferelectrodes V1, V2, V3, V4, V5 and V6 are repeatedly arranged in orderfrom the left side on the drawing, the first phase vertical transferpulse φV1 to the transfer electrode V1, the second phase verticaltransfer pulse φV2 to the transfer electrode V2, the third phasevertical transfer pulse φV3 to the transfer electrode V3, the fourthphase vertical transfer pulse φV4 to the transfer electrode V4, thefifth phase vertical transfer pulse φV5 to the transfer electrode V5 andthe sixth phase vertical transfer pulse φV6 to the transfer electrode V6are applied, respectively. Then, as shown in FIG. 6, when the verticaltransfer pulses φV1 to φV6 are turned on and a high voltage is appliedto each of the transfer electrodes V1 to V6, the electric potentialunder the corresponding transfer electrode becomes deep to form a chargepacket. Further, when the vertical transfer pulses φV1 to φV6 are turnedoff and a low voltage is applied to each of the transfer electrodes V1to V6, the electric potential under the corresponding transfer electrodebecomes shallow to form a potential barrier.

At time T0, by applying the high voltage to the transfer electrode V1and by applying the low voltage to the transfer electrodes V2, V3, V4,V5 and V6, the electric potential under the transfer electrode V1 isdeep, and the electric potential under the transfer electrodes V2 to V6become shallow; and a charge pocket is formed under the transferelectrode V1 to store the signal electric-charge and barriers are madeunder the transfer electrodes V2 to V6 to prevent the signal beingmixed. The packet size to store electric-charge is made of twoelectrodes.

Next, at time T1, the transfer electrode V2 becomes the high electricpotential with maintaining the transfer electrode V1 in the high voltagehaving the charge packet formed under the electrode, and withmaintaining the transfer electrodes V3 to V6 in the low electricpotential having the barriers formed. Accordingly, since the electricpotential under the electrode V2 becomes deep, the charge packet isformed with the two electrodes of V1 and V2, and the signalelectric-charge previously stored under the transfer electrode V1 (atthe time T0) also moves to the side of the transfer electrode V2.

At time T2, the transfer electrode V1 becomes the low electric potentialwith maintaining the transfer electrode V2 in the high voltage havingthe charge packet formed under the electrode, and with maintaining thetransfer electrodes V3 to V6 in the low electric potential having thebarriers formed. Accordingly, since the electric potential under theelectrode V1 becomes shallow, all the signal electric-charge under thetransfer electrode V1 moves to the position under the transfer electrodeV2, where the signal electric-charge is stored.

At time T3, the transfer electrode V3 becomes the high electricpotential with maintaining the transfer electrode V2 in the high voltagehaving the charge packet formed under the electrode, and withmaintaining the transfer electrodes V4 to V6 in the low electricpotential having the barriers formed. Accordingly, since the electricpotential under the electrode V3 becomes deep, the charge packet isformed with the two electrodes of V2 and V3, and the signalelectric-charge under the transfer electrode V2 also moves to the sideof the transfer electrode V3.

At time T4, the transfer electrode V2 becomes the low electric potentialwith maintaining the transfer electrode V3 in the high voltage havingthe charge packet formed under the electrode, and with maintaining thetransfer electrodes V4 to V6 in the low electric potential having thebarriers formed. Accordingly, since the electric potential under theelectrode V2 becomes shallow, all the signal electric-charge under thetransfer electrode V2 moves to the position under the transfer electrodeV3, where the signal electric-charge is stored.

At time T5, the transfer electrode V4 becomes the high electricpotential with maintaining the transfer electrode V3 in the high voltagehaving the charge packet formed under the electrode, and withmaintaining the transfer electrodes V1, V2, V5 and V6 in the lowelectric potential having the barriers formed. Accordingly, since theelectric potential under the electrode V4 becomes deep, the chargepacket is formed with the two electrodes of V3 and V4, and the signalelectric-charge stored under the transfer electrode V3 also moves to theside of the transfer electrode V4.

At time T6, the transfer electrode V3 becomes the low electric potentialwith maintaining the transfer electrode V4 in the high voltage havingthe charge packet formed under the electrode, and with maintaining thetransfer electrodes V1, V2, V5 and V6 in the low electric potentialhaving the barriers formed. Accordingly, since the electric potentialunder the electrode V3 becomes shallow, all the signal electric-chargesunder the transfer electrode V3 moves to the position under the transferelectrode V4, where the signal electric-charge is stored.

The signal electric-charge under the transfer electrode V1 istransferred to the position below the transfer electrode V4 by theseries of driving from the time T1 to the time T6. The period of time T1to time T6 is approximately half a cycle of the vertical transfer pulsesφV1 to φV4.

Subsequently, at time T7, the transfer electrode V5 becomes the highelectric potential with maintaining the transfer electrode V4 in thehigh voltage having the charge packet formed under the electrode, andwith maintaining the transfer electrodes V1, V2, V3 and V6 in the lowelectric potential having the barriers formed. Accordingly, since theelectric potential under the electrode V5 becomes deep, the chargepacket is formed with the two electrodes of V4 and V5, and the signalelectric-charge under the transfer electrode V4 also moves to the sideof the transfer electrode V5.

At time T8, the transfer electrode V4 becomes the low electric potentialwith maintaining the transfer electrode V5 in the high voltage havingthe charge packet formed under the electrode, and with maintaining thetransfer electrodes V1, V2, V3 and V6 in the low electric potentialhaving the barriers formed. Accordingly, since the electric potentialunder the electrode V4 becomes shallow, all the signal electric-chargesunder the transfer electrode V4 moves to the position under the transferelectrode V5, where the signal electric-charge is stored.

At time T9, the transfer electrode V6 becomes the low electric potentialwith maintaining the transfer electrode V5 in the high voltage havingthe charge packet formed under the electrode, and with maintaining thetransfer electrodes V1 to V4 in the low electric potential having thebarriers formed. Accordingly, since the electric potential under theelectrode V6 becomes deep, the charge packet is formed with the twoelectrodes of V5 and V6, and the signal electric-charge under thetransfer electrode V5 also moves to the side of the transfer electrodeV6.

At time T10, the transfer electrode V5 becomes the low electricpotential with maintaining the transfer electrode V6 in the high voltagehaving the charge packet formed under the electrode, and withmaintaining the transfer electrodes V1 to V4 in the low electricpotential having the barriers formed. Accordingly, since the electricpotential under the electrode V5 becomes shallow, all the signalelectric-charges under the transfer electrode V5 moves to the positionunder the transfer electrode V6, where the signal electric-charge isstored.

At time T11, the transfer electrode V1 becomes the low electricpotential with maintaining the transfer electrode V6 in the high voltagehaving the charge packet formed under the electrode, and withmaintaining the transfer electrodes V2 to V5 in the low electricpotential having the barriers formed. Accordingly, since the electricpotential under the electrode V1 becomes deep, the charge packet isformed with the two electrodes of V6 and V1, and the signalelectric-charge under the transfer electrode V6 also moves to the sideof the transfer electrode V1.

At time T12, the transfer electrode V6 becomes the low electricpotential with maintaining the transfer electrode V1 in the high voltagehaving the charge packet formed under the electrode, and withmaintaining the transfer electrodes V2 to V5 in the low electricpotential having the barriers formed. Accordingly, since the electricpotential under the electrode V6 becomes shallow, all the signalelectric-charges under the transfer electrode V6 moves to the positionunder the transfer electrode V1, where the signal electric-charge isstored.

The signal electric-charge under the transfer electrode V4 istransferred to the position below the transfer electrode V1 by theseries of driving from the time T7 to the time T12. The period of timefrom time T7 to time T12 is approximately half a cycle of the verticaltransfer pulses φV1 to φV6.

Then, as understood from the above, the signal electric-charge storedunder the transfer electrode V1 at time T0 is transferred by the seriesof driving from the time T0 to the time T12 to the position under thetransfer electrode V1 which is away only by a pixel. Then, theelectric-charge transfer at the time T6 is in the state of 180 degreesshifted (reverse phase) compared to that at the time T12 (equivalent toT0). In addition, between the time T2 and the time T6 or between thetime T4 and T8, the electric-charge transfer is in the state of 180degrees shifted to each other.

Therefore, according to the above, the electric-charge transfer for oneelectrode can be executed by the ⅙ cycle (60 degrees phase difference)of the six-phase drive, and the electric-charge transfer for twoelectrodes can be executed by the ⅓ cycle (120 degrees phasedifference), and the electric-charge transfer for the three electrodescan be executed by the ½ cycle (180 degrees phase difference) and theelectric-charge transfer for six electrodes can be executed by onecycle.

In other words, in this drive method, with respect to each dummyvertical CCD 132 of the odd column and the even column, the differenceby three vertical transfer electrodes (three registers) is provided, sothat even if the vertical transfer electrodes V1 to V6 are used incommon for the odd column and the even column, the state of the signalelectric-charge of the phases having 180 degrees difference reaching theelectric-charge detection unit 210 can be obtained.

Further, when the signal electric-charge of the odd column reaches thefloating diffusion FD through one cycle (T1 to T12 shown in FIG. 6) ofthe vertical transfer pulses of φV1 to φV6, the signal electric-chargeof the even column has not reached yet. On the contrary, when the signalelectric-charge of the even column reaches the floating diffusion FD,the signal electric-charge of the odd column has not reached yet.

Therefore, in the state in which a selective gate voltage VOG is fixed,the read-out of the odd column is completed by vertically transferringthe signal electric-charge from time T1 to T6 and by scanninghorizontally. Next, after a reset gate pulse φRG is turned on and thefloating diffusion FD is cleared, the read-out of the even column iscompleted by vertically transferring the signal electric-charge in therest of the time from T7 to T12 and by scanning horizontally. Byrepeating such processing, the pixel signal in time series correspondingto the signal electric-charge of one screen (the whole of the imagepick-up area 100) can be output from the output signal wire 290.

Further, as assumed from the above, in order to obtain the state inwhich electric-charge transfer has 180 degrees difference (reversephase), vertical transfer electrodes V1 to V6 may not be shared, but thevertical transfer electrodes V1 to V6 which can be driven independentlyfor each of the odd column and the even column may be used. In thiscase, the dummy vertical CCD 132 becomes unnecessary and vertical CCDmay have the same length. However, it is necessary to make the layout(formation) of the vertical transfer electrodes V1 to V6 for the oddcolumn and the even column independently. Therefore, the patterning onthe vertical transfer electrode side becomes difficult.

FIGS. 7 and 8 are the drawings explaining an example in which thearrangement of the vertical transfer electrodes V1 to V6 is changed tosolve the above problem and to make electric-charge transfer have areverse phase. In this example, the vertical transfer electrodes V1 toV4 are shared and the dummy vertical CCD 132 is not provided, and thephase of electric-charge transfer is made to become a reverse phase whenthe signal electric-charge of the photo-conductive units 120 in the samerow reaches the electric-charge detection unit 210. As shown in FIG. 8A,with respect to the odd column and the even column the arrangement ofthe vertical transfer electrodes V1 to V6 in the same row is made tohave a reverse phase. In order to obtain such patterning, the patterningas shown in FIG. 8B of schematic zigzag-shape may be performed.

With the above configuration, the signal electric-charge can betransferred with reverse phase to the side of the floating diffusion FD,with sharing the various electrodes such as the vertical transferelectrodes V1 to V6, the electrode used for the selective gate VOG andothers, using the common vertical transfer pulses φV1 to φV6 for the oddcolumn and for the even column, and without providing the dummy verticalCCD 132. Namely, when the signal electric-charge of the odd columnreaches the floating diffusion FD, the signal electric-charge of theeven column has not reached yet. On the contrary, when the signalelectric-charge of the even column reaches the floating diffusion FD,the signal electric-charge of the odd column has not reached yet.

FIG. 9 is a timing chart that explains the vertical transfer andread-out in the horizontal direction in the case where the CCD solidstate image sensor of the first embodiment is used and that shows thewhole operation from electric-charge transfer in the vertical directionuntil obtaining the pixel signal of time series from the output signalwire 290 in one horizontal scanning cycle.

As described above, the register (charge packet) corresponding to eachof the transfer electrodes V1 to V6 of the vertical CCD and the dummyvertical CCD 132 is driven by the completely the same vertical transferpulses φV1 to φV6. Further, the reset gate pulse φRG is used accordinglyfor the odd column and the even column in common, because thecorresponding electrode is formed in common.

In the period of each read-out cycle of the odd column or of the evencolumn in one horizontal cycle shown in FIG. 9, by driving the verticaltransfer pulses φV1 to φV6 with the timing shown in the drawing, eachsignal electric-charge of the odd column and even column which is storedin the register below the vertical transfer pulses φV1 to φV6 issequentially transferred in parallel (at the same time) to the side ofthe dummy vertical CCD 132. The electric-charge of each column which hasbeen transferred to the register corresponding to the pixel of the finalstage of the vertical CCD 130 is transferred to the floating diffusionFD of the electric-charge detection unit 210 through the dummy verticalCCD 132.

Accordingly, the electric-potential of the floating diffusion FDchanges, and that electric-potential is detected through a sourcefollower type amplifier not shown in the drawing. After the signalelectric-charge is detected, a reset gate wire (electrode) RG is turnedon by the reset gate pulse φRG, and the electric-potential of thefloating diffusion FD is reset to the voltage V_(RD) of reset drainwhich is an N+ region.

Hereupon, the register (charge packet) of the odd column has thethree-stage difference from that of the even column in the dummyvertical CCD 132, and the signal electric-charge is made to reach thefloating diffusion FD with 180 degrees difference (inverse phase) in onecycle of the vertical transfer pulses φV1 to φV6 (T1 to t12 shown in thedrawing). Therefore, when the signal electric-charge of the odd columnreaches the floating diffusion FD, the signal electric-charge of theeven column has not reached yet. On the contrary, when the signalelectric-charge of the even column reaches the floating diffusion FD,the signal electric-charge of the odd column has not reached yet.

Therefore, when vertical transfer pulses φV1 to φV6 are driven by theillustrated timing at the timings of T1 to T12, at time T6 in the oddcolumn read-out cycle (T1 to T7) of the first half, the signalelectric-charge of the odd columns of A, C, E . . . is transferred tothe floating diffusion FD; is converted to the voltage signal in theelectric-charge detection unit 210 (the electric-charge is read out);and is input to the column selection unit 270 through the band-limitunit 230 and the CDS processing unit 250. During the time between T6 andT7, an image signal of the time series corresponding to the signalelectric-charge of the odd columns such as columns A, C, E . . . in oneline is output to the output signal wire 290 by the control of thecolumn selection pulse SP (n) over the column selection unit 270, thatis, by the horizontal scanning by means of the column selection pulsegenerator 280.

Here, because the length of the odd columns A, C, D . . . is differentfrom that of the dummy vertical CCD 132 of the even columns B, D, F . .. such that the phase of electric-charge transfer rotates 180 degrees,so that at the time T6 when the electric-charge of the odd columns A, C,E . . . reaches the floating diffusion FD in the odd column read-outcycle of the T1 to T7, the signal electric-charge of even columns B, D,F . . . has not reached the floating diffusion FD.

After the horizontal scanning by the column selection pulse generator280 until the time T7, the switch of the reset gate RG is turned on bythe reset gate pulse φRG, and after the electric potential of thefloating diffusion FD is returned to the reset level and the floatingdiffusion FD is cleared, the switch of the reset gate is turned off.

Then, when the vertical transfer pulses φV1 to φV6 are driven by theillustrated timing in each of the timings T7 to T1 of the even columnread-out cycle of the second half, similarly to the above describedoperation of columns A, C, E . . . the signal electric-charge of evencolumns B, D, F . . . start to be transferred, and reaches the floatingdiffusion FD at the time T12. At this time, the signal electric-chargeof the odd column has not reached the floating diffusion FD yet, becausethe phase of the electric-charge transfer thereof has the 180-degreedifference.

After transferred to the floating diffusion FD, the signalelectric-charge of the even column is converted into the voltage signalin the electric-charge detection unit 210 (the signal electric-charge isread out), and then is input to the column selection unit 270 throughthe band-limit unit 230 and the CDS processing unit 250. During the timebetween T12 and T1 of the next horizontal scanning cycle, an imagesignal of the time series corresponding to the signal electric-charge ofthe odd columns such as A, C, E . . . , in one line is output to theoutput signal wire 290 by the control of the column selection pulse SP(n) over the column selection unit 270, that is, by the horizontalscanning by the column selection pulse generator 280.

Therefore, as shown in the drawing, the processing of the output of theodd column image signal to the output signal wire 290 being completedand the output of the even column image signal to the output signal wire290 being completed is repeatedly performed, so that the pixel signal oftime series corresponding to the signal electric-charge for onehorizontal scanning cycle can be output from the output signal wire 290.Then, with repeating sequentially the processing with respect to onehorizontal scanning cycle, the image signal corresponding to the signalelectric-charges for one screen can be output from the output signalwire 290.

As described above, since a plurality of adjacent columns (an odd columnand even column in the above embodiment) of the vertical CCDs areassigned as a group to one electric-charge detection unit, in which thenumber of stages included in each column is changed, each signalelectric-charge of the odd column and of the even column can besequentially read out to the side of the electric-charge detection unitin time series. Then, when the floating diffusion FD is for example usedas the electric-charge detection unit 210, the number of wiringconnected to the selective gate VOG can be reduced by providing theselective gate VOG for the plurality of columns (an odd column and evencolumn in the above embodiment) in common, and the area can be usedeffectively, for example, in view of incorporating the CDS processingunit 250, and others. Further, the number of circuits existingsubsequently to an electric-charge detection unit 210 is required to bethe same number as the electric charge detection units 210, and thenumber can be reduced because a plurality of columns (an odd column andeven column in the above embodiment) are made into one group, so thatthe electric power consumption can be reduced.

FIGS. 10A and 10B are diagrams showing a first example of theconfiguration for one unit of operation with respect to theelectric-charge detection unit 210, the band-limit unit 230, the CDSprocessing unit 250 and the column selection unit 270 in the read-outprocessing unit 200. FIG. 10A is a circuit diagram and FIG. 10B is atiming chart that explains the operation thereof.

In this read-out processing unit 200, the electric-charge detection unit210 constitutes a prior stage output unit (pre-amplifier) incorporatedin the CCD solid state image sensor 10; has a source follower (currentamplifier circuit) structure having a drive MOS transistor (DM: DriveMOS) DM and a load MOS transistor (LM; Load MOS) LM; and includes a MOStransistor having a reset gate terminal which is controlled based on thereset gate pulse φRG and a function of converting the signalelectric-charge from the vertical CCD 130 into the voltage signal. Notethat though one stage source follower is used in the diagram, pluralstages of source followers may be used.

The gate of the drive MOS transistor DM is connected to the floatingdiffusion FD in which the signal electric-charge supplied from verticalCCD 130 through the selective gate VOG is accumulated and a source ofthe MOS transistor RGTr used for the reset gate RG is connected to thereset drain power source VRD to discharge the signal electric-charge.The floating diffusion FD is connected to the vertical CCDs 130 of twocolumns of an odd column (odd) and an even column (even) to constitutethe floating diffusion amplifier FDA. The reset drain power source VRDcan be shared with the power source V_(DD).

In the electric-charge detection unit 210, a predetermined selectivegate voltage V_(OG) is applied to the selective gate VOG and the resetgate pulse φRG is applied to the reset gate wire RG in the signalelectric-charge detection cycle. Then, the signal electric-chargeaccumulated in the floating diffusion FD is converted into the signalvoltage and is output as the pixel signal through the output circuit ofthe source follower structure including the drive MOS transistor DM andload MOS transistor LM.

Then, the signal electric-charge stored immediately before a certaintime in the gate capacity of the first stage source follower is resetwhen a pulse is applied to the reset gate wire RG. At this time, aterminal A becomes a reset electric-potential. With respect to a pointB, the reset electric-potential is fixed after the delay by a timeconstant which is determined by the output impedance of the first stagesource follower and a band-limit capacity Cout. When the resetelectric-potential is fixed at the point B, a pulse is input to a clamppulse CLP and the reset electric-potential is clamped.

Next, the signal electric-charge is input to the terminal A by the inputpulse. Then, the electric-potential drops to the extent of the signalelectric-charge at the terminal A. Further, at the point B, similarly tothe time when resetting, the signal electric-potential is fixed afterthe delay by the time constant. At this time, a pulse is applied to ahold pulse HP, and the electric-potential at that time is stored in apoint C. The electric-potential of the difference between the signalelectric-potential and the reset electric-potential is stored in thepoint C.

Subsequently, the image signal is output to the output signal wire 290by supplying a column selection pulse SP (n) to a column selection unit270 by a column selection pulse generator 280. In this operation, aperiod of time when detecting the signal electric-potential and a periodof time when detecting the reset electric-potential are made equal. Thisis because when the difference between the signal electric-potential andthe reset electric-potential is obtained in the CDS processing unit 250at the subsequent stage, two electric potentials are required to berestricted by the same bandwidth to have the noise component of the samelevel. In other words, it is because a noise component becomes large inthe signal in which the difference is obtained, even if one of the twosignals has a low noise component.

With the above configuration, since the bandwidth can be restricted by alow pass filter composed of the output impedance of the first stagesource follower and the band-limit capacity Cout, the noise componentcontained in the output signal can be made small. Further, the read-outprocessing unit 200 incorporates the CDS processing unit 250 whichdetects the difference (difference in the output) between the resetelectric-potential of the period virtually without a signalelectric-charge and the signal electric-potential of the periodvirtually with a signal electric-charge, so that at the same time thereset noise which occurs in the dispersion of the electric-potentialwhen the electric-charge of immediately before the time is reset and afixed pattern noise (FPN) can also be suppressed using the CDS(correlation double samplings) function; and a signal with excellent S/Ncan be obtained. Note that the density unevenness caused by thedifference of the conversion gain in the electric-charge detection unit210 becomes comparatively high frequency, so that the density unevennesson the screen can be invisible not to cause a problem.

Moreover, similarly to the electric-charge detection unit 210, oneband-limit unit 230 and one CDS processing unit 250 are only required tobe provided with respect to the plurality of columns (two columns inthis embodiment) of the vertical CCD 130, which contributes to thereduction of the sensor area and electric power consumption. Inaddition, since a CDS circuit need not have a structure of beingattached to the outside, peripheral circuits can also be reduced.

Though the electric-charge detection unit 210 and others are providedfor every two vertical CCDs 130 in the above configuration, needless tosay, one electric-charge detection unit 210, one CDS processing unit 250and others may be provided for every three or more vertical CCDs 130,and may be used with further time sharing. With this configuration,since the total number of the electric-charge detection units 210, theCDS processing units 250 and other units can further be reduced, thesensor area and the electric power consumption can be reduced all themore.

Further, a selective gate VOG can be omitted in the configuration ofFIG. 2.

The electric-charge detection unit 210 shown in FIG. 10A is constructedusing the floating diffusion; however, the configuration is not limitedthereto and, for example, a floating gate (refer to; ISSCC Digest ofTechnical Papers, 197391, pp. 154-155) can be used. When the floatinggate is used, the signal not having a direct current can be obtained, sothat the operation point can easily be set at around half the powersupply voltage in the next stage amplifier.

FIG. 11 is a circuit diagram showing a second example of theconfiguration for one unit of operation with respect to theelectric-charge detection unit 210, the band-limit unit 230, the CDSprocessing unit 250 and the column selection unit 270 in the read-outprocessing unit 200. In the second example of the configuration, thecircuit subsequent to the electric-charge detection unit 210 is dividedinto two systems such as a signal component detection system and a resetnoise component detection system to perform processing. In other words,this configuration is characterized in that a first band-limit unit 230a having band-limit capacity Ca and a second band-limit unit 230 bhaving a band-limit capacity Cb are used to separately restrict thesignal component and the reset noise component.

A signal component selection MOS transistor 220 a is arranged betweenthe electric-charge detection unit 210 and the band-limit unit 230 a ofthe signal component detection system, and the band-limit unit 230 a hasa band-limit capacity Ca used for the signal component. A columnselection MOS transistor 222 a used for the signal component is arrangedbetween the band-limit unit 230 a and the output signal wire 290.Further, a reset noise component selection MOS transistor 220 b isarranged between the electric-charge detection unit 210 and theband-limit unit 230 b of the reset noise component detection system, andthe band-limit unit 230 b has a band-limit capacity used for the resetnoise component. A column selection MOS transistor 222 b used for thereset noise component is arranged between the band-limit unit 230 b andthe output signal wire 290. The electric-charge detection unit 210 andthe vicinity thereof are similar to the first example of theconfiguration.

In the operation of the second configuration, when the signal componentis being input into the terminal A, the signal component selection MOStransistor 220 a is turned on; and when the reset noise component isbeing input into the terminal A, the reset noise component selection MOStransistor 220 b is turned on. Then, the signal component accumulates inthe band-limit capacity Ca used for the signal component, and the resetnoise component accumulates in the band-limit capacity Cb used for thereset noise component. Further, when a column is selected, the columnselection MOS transistor 222 b for the reset noise component and thecolumn selection MOS transistor 222 a for the signal component areturned on sequentially. As a result, the reset noise component and thesignal component are sequentially output to the output signal wire 290and are input into the CDS circuit attached on the outside.

The noise which occurs in the CDS circuit depends on a clamp capacity CLand a hold capacity Ch shown in FIG. 10. If each capacity is enlarged asmuch as possible, the noise which occurs becomes small. In the secondexample of the configuration, a reset noise component and a signalcomponent are sequentially output, so that the CDS processing can beperformed on the outside. Since the CDS processing is performed on theoutside, each value of the clamp capacity CL and the hold capacity Chcan be enlarged to make the noise which occurs in the CDS circuit small.

FIGS. 12A and 12B are block diagrams showing an example of the wholeconfiguration of the image pick-up device 20 including the signalprocessing circuit connected subsequently to the read-out processingunit 200. Hereupon, the system block diagram to reproduce a picture fromthe image pick-up device 20 using the CCD solid state image sensor 40 ofthe first embodiment is shown.

A signal processing unit 300 is connected to the output signal wire 290and includes: an A/D converter 310 which converts an analogue imagesignal into digital image data, a picture memory unit (field memory) 320which stores the digital image data by the unit of one screen, and amemory control unit 330 which controls the write-in and read-out of thedata of the picture memory unit 320. A row adjustment unit according tothe present invention is composed of the picture memory unit 320 and thememory control unit 330. Specifically, the function as the rowadjustment unit, which obtains the image signal aligned in order in thehorizontal direction, is obtained by rearranging each pixel signal ofeach image signal of the odd column and even column, which is outputfrom the read-out processing unit 200 in the direction of the rowcorresponding to the arrangement of the row and the column.

The signal processing unit 300 further includes: a D/A converter 340which converts the video data read out from the picture memory unit 320into the analogue signal, an NTSC converter 350 which generates based onthe video signal converted to the analogue signal by the D/A converter340 an NTSC signal that is an example of the broadcast format, and adisplay 360 which displays the visible picture based on the NTSC signaloutput from the NTSC converter 350.

In this configuration, the signal electric-charge converted by thephoto-electric conversion in the photo-conductive unit 120 isrespectively read out to the corresponding vertical CCD 130. The signalelectric-charge read out to the vertical CCD 130 is sequentiallytransferred in parallel to the electric-charge detection unit 210through the floating diffusion in the time sharing with a plurality ofadjacent lines as a group.

The signal electric-charge of each column transferred to theelectric-charge detection unit 210 is converted into the voltage signalin the electric-charge detection unit 210; an offset noise and a fixedpattern noise are controlled by a CDS processing unit 250; and the imagesignal corresponding to each photo-conductive unit 120 in the imagepick-up area 100 is output in time series from the output signal wire290 by the horizontal scanning function of the column selection pulsegenerator 280 with respect to the column selection unit 270.

The image signal corresponding to each photo-conductive unit 120, whichis output in time series from the output signal wire 290, is input intothe signal processing unit 300, and the A/D conversion is performed toconvert the signal by the A/D converter 310 and the signal is stored inthe picture memory unit 320. A memory control unit 330 is connected tothe picture memory unit 320, and the address setting of memory area andthe control over the order of the read-out and so on are performed.

In the case of the CCD solid state image sensor 40 of the firstembodiment, each signal electric-charge of the odd column and the evencolumn of the vertical CCDs 130 is transferred to the read-outprocessing unit 200 in the time sharing, and after converted into thevoltage signal, the image signal corresponding to each photo-conductiveunit 120 in the image pick-up area 100 is made to be in time series by ahorizontal scanning function of the column selection pulse generator 280with respect to the column selection unit 270. Therefore, in everyhorizontal scanning cycle, in the horizontal scanning cycle of the firsthalf, the image signal in time series for the odd column is only outputfirst, and subsequently, in the horizontal scanning cycle of the lasthalf, the image signal in time series for the even column is onlyoutput.

The image signal in which the odd column and the even column are outputin the time sharing is digitized and sent to the side of the picturememory unit 320, and the memory control unit 330 sets the address of thepicture memory unit 320 at the read-in time to correspond to the pixelposition of the image pick-up area 100, so that the picked-up pictureinformation in the image pick-up area 100 is made to have the samearrangement as the picture information in the picture memory unit 320.

Accordingly, the picture data corresponding to the signalelectric-charge in the odd column in the vertical CCD 130 is stored in,for example, storage areas 320-1 to 320-(2 n-1), and the picture datacorresponding to the signal electric-charge in the even column in thevertical CCD 130 is stored in storage areas 320-2 to 320-(2 n).

When the picture is reproduced, the picture data is sequentially readout from the storage areas 320-1 to 320-2 n within the picture memoryunit 320 as the serial data, and is displayed in a display 360 throughthe D/A converter 340 and the NTSC converter 350.

It should be noted that, in the above described example, the write-inposition at the time of storing the data in the picture memory unit 320is controlled by the memory control unit 330 so that the image pictureinformation in the image pick-up area 100 and the picture information ofthe picture memory unit 320 have the same arrangement; however, thecontrol can be performed at the read-out time instead of the write-intime. Specifically, as shown first in FIG. 12B, in the schematic view ofthe storage area of the picture memory unit 320, the storage area of thepicture memory unit 320 is divided into the odd column area and the evencolumn area, and the input data from the A/D converter 310 with respectto the odd column and the even column are stored sequentially in eachstorage area at the write-in time in order of data input. Then, at theread-out time the data of the odd column and of the even column A, B, C,D is alternately read out in each horizontal scanning cycle from thedivided odd column area and the even column area, and is supplied to theD/A converter 340. Accordingly, the image picture information in theimage pick-up area 100 and the picture on the display 360 can be made tohave the same arrangement.

Further, although not shown in the drawings, instead of using a fieldmemory as the picture memory unit 320, when with respect to each of theodd column and the even column a shift register (FIFO memory) havingstages corresponding to the pixel number of half a line and a selectioncircuit to switch the shift register are used, data can be convertedinto the signal in time series of one horizontal line which is arrangedin order of image picture information in the image pick-up area 100(data can be rearranged to be aligned in order in the horizontaldirection).

As described-above, according to the image pick-up device 20 of thefirst embodiment, the problem in which the clock frequency of ahorizontal CCD reaches a limit when the pixel number of the CCD solidstate image sensor increases can be solved without using horizontal CCD,such that signal electric-charge is transferred to the electric-chargedetection unit (in the above embodiment, to an amplifier FDA using thefloating diffusion) in the time sharing with a plurality of verticalCCDs as one group and is converted into the voltage signal in theelectric-charge detection unit, and after that, the voltage signal inthe vertical line is sequentially selected in the horizontal directionand is read out. The rearrangement of the data series by reading out avertical line in the time sharing can be performed with a comparativelysimple circuit, which can avoid a problem.

In addition, although the time sharing is employed, the sensitivitydecline per pixel caused by the high density pixels can be complementedusing the signal of adjacent pixels (or of the same color pixelpositioned away by two pixels), because the signal electric-charge canbe read out per vertical CCD.

Further, when a plurality of columns of the vertical CCDs, are connectedto the electric-charge detection unit (in the above embodiment thefloating diffusion amplifier FDA) as a group, the length of the verticalCCD, namely, the number of stages of the register (packet) defined bythe vertical transfer electrode is changed with respect to the column,and the phase of electric-charge transfer when reaching theelectric-charge detection unit is made invert, so that even if avertical transfer electrode is shared, signal electric-charge can beread out to the electric-charge detection unit using one selective gateinstead of using a plurality thereof (in the above example two) for theselection of the column CCD. As a result, the number of wiring aroundthe electric-charge detection unit can be reduced, and the area can beused efficiently in view of incorporating the CDS circuit and othercircuits with respect to the miniaturization of the solid state imagesensor.

Further, although a time sharing is employed, since the electric-chargedetection unit is provided virtually for each vertical CCD, only signalsof several times (the same number as the columns which oneelectric-charge detection unit takes charge) are input to the electriccharge detection unit in one horizontal scanning cycle and the frequencybandwidth of the signal becomes considerably small. Hence, the frequencybandwidth of the amplifier which constitutes the electric-chargedetection unit can be restricted using the low pass filter. As a result,the band of the heat noise which occurs in the transistor at the sametime can be restricted and a noise component can be made small. Further,since the signal bandwidth can be lowered, a noise bandwidth can be madenarrow accordingly by the band-limit unit and the picture having anexcellent S/N ratio can be obtained.

FIGS. 13 and 14 are drawings which explain modified examples of the CCDsolid state image sensor 40 of the first embodiment and are schematicplan views showing the vicinity of the boundary portion of the verticalCCD 130 and the read-out processing unit 200. Hereupon, in the firstmodified example shown in FIG. 13 two sets of adjacent columns furtherbecome one group, in which the arrangement of the number of stages ofthe dummy vertical CCDs 132 is made to alternate with respect to the twosets, the electrode for the adjacent selective gate VOG is connected,and the output wire is shared.

That is, with the center line of two sets performed as the boundary, thenumber of stages of the dummy vertical CCD 132 is made to changesequentially corresponding to the distance from the center line.Further, in the first modified example shown in FIG. 13, an adjacentreset gate wire is connected to a center line of the different positionfrom the center line of the above-mentioned two sets, and the outputwire can be shared. According to the first modified example, theelectrodes for the selective gate VOG and the reset gate are connectedbetween adjacent sets, so that the number of output wires can further bereduced.

Further, in FIG. 13, for example, two sets of adjacent columns A and Band adjacent columns C and D are made one group, and two sets ofadjacent columns C and D and adjacent columns E and F are made onegroup; and the electrode for the selective gate VOG is connected betweenthe columns B and C, and the reset gate wire is connected between thecolumns D and E. However, other grouping than the above can be employed.

For example, two sets of columns C and D and columns E and F may be madeone group, respectively and an electrode for the selective gate VOG canbe connected in the same way between the columns D, E. The secondmodified example shown in FIG. 14 is an example further developed fromthe above example, in which all the electrodes for the selective gateVOG are connected and the output wires of the selective gate can furtherbe reduced. In this case, fundamentally the number of output wires isone; however, the problem of wire resistance occurs. Therefore, it ispreferable that the position where the electrode and the output wire forthe selective gate VOG are installed is practically decided inconsideration of a balance between the wire resistance and thedifficulty of wiring.

FIG. 15 is a diagram which explains a modified example of the timingchart when the vertical transfer pulses φV1 to φV4 of the four-phasedrive is used and explains the positional relationship between theelectrode and the signal electric-charge in the CCD solid state imagesensor of the first embodiment. This modified example is characterizedin that each of the vertical transfer pulses φV1 to φV4 is driven with90 degrees shifted. The other configuration than the transfer electrodesV1 to V4 to which the vertical transfer pulses φV1 to φV4 for thefour-phase drive are applied is the same as FIG. 1.

The following advantage can be obtained in this modified example, asunderstood from FIG. 15, with respect to the positional relationshipbetween the electrode and the signal electric-charge. Specifically, withrespect to the odd column, when the signal electric-charge of the packetV4 is transferred to the floating diffusion FD, the packet V2 of therelevant even column acts as a barrier during a period of time t1.Further, with respect to the even column, when the signalelectric-charge of the packet V2 is transferred to the floatingdiffusion FD, the packet V4 of the relevant odd column acts as a barrierduring a period of time t2.

In addition, in this modified example, when an accumulation packet sizeis small, the power supply voltage VDD is raised to obtain the depth ofthe voltage potential and the problem can be solved.

FIGS. 16A and 16B are diagrams which explain the CCD solid state imagesensor 40 of the third embodiment. In this third embodiment, twoadjacent vertical CCDs as one set are assigned to one electric-chargedetection unit, which is common to the CCD solid state image sensor 40of the first embodiment; however, in this embodiment the dummy verticalCCD 132 is not provided and the number of stages of the vertical CCDsremains the same. That is, two columns of vertical CCDs 130 are read outto the electric-charge detection unit 210 having the configuration of afloating diffusion FDA.

As shown in FIG. 16A, since the wiring of the selective gate VOG can beconnected from the opposite side to each vertical CCD 130 with thefloating diffusion in between, the restriction in the wiring decreases,compared with the configuration in which three or more as a group areassigned to one electric-charge detection unit 210 and the problem ofthe wiring space to the selective gate VOG in the center portion occurs,and problems can be avoided comparatively even in the actual pattern.

However, as shown in FIG. 16B, since the fact that the same number ofwiring for the selective gate of the vertical CCD 130 is required asthat of the vertical CCDs 130 remains unchanged, the ratio of occupyingwiring to the area becomes larger than that of the first or the secondembodiment.

The present invention has heretofore been explained using theembodiments; however, the scope of the present invention is not limitedto the above-mentioned embodiments. Various changes or improvement canbe added to the above embodiments within the range not departing fromthe spirit of the invention, and embodiments to which such changes orimprovement is applied are also included in the scope of this invention.

Moreover, the invention described in appended claims is not limited bythe above-described embodiments, and all the combinations of thecharacteristics being explained in the embodiments are not necessarilyindispensable for the solution means of the invention. In theabove-mentioned embodiments, invention of various stages is included andvarious kinds of invention can be extracted by appropriately combiningthe plurality of disclosed constituents. Even if some constituents aredeleted from all constituents shown in the embodiments, theconfiguration from which those constituents are deleted can be extractedas an invention, as long as the effectiveness thereof can be obtained.

For example, though an example suitable for the six electrodes/six-phasedrive and the four electrodes/four-phase drive is explained in theabove-mentioned embodiments, the number of the vertical transferelectrodes and the relationship with the phases of the transfer pulsesare not limited to ones having the above-mentioned timing. Moreover, notlimited to two columns and three columns, more columns can be assignedto one electric-charge detection portion with respect to the relationswith the transfer pulses.

In other words, when a plurality of adjacent columns are assigned to oneelectric-charge detection unit, the number of stages in the dummyvertical transfer unit (virtually the same as the vertical CCD), thearrangement of the vertical transfer electrodes and the timing of thevertical transfer pulses are changed such that each signalelectric-charge in the same row reaches the electric-charge detectionunit in a different phase to each other. The number of stages in thedummy vertical transfer portion and the arrangement of the verticaltransfer electrodes are the same, and only a drive method may bedifferent, in other words, only the timing of the transfer pulse can bedifferent, which is also acceptable.

Moreover, although explanation is made in the above-mentionedembodiments using the CCD solid state image sensor of the inter-linetransfer type, the present invention is not limited thereto and may beapplied to a CCD solid state image sensor of the other transfer methodssuch as the frame inter-line transfer type, the full frame transfer typeand the frame transfer type.

Furthermore, other types of electric-charge transfer unit than the abovecan also be used such that with respect to the vertical transferportion, CCD is replaced with CSD (charge sweeped device), for example.

1. A solid state image sensor comprising: a plurality ofphoto-conductive units which are arranged in each direction of the rowand the column in the two-dimensional shape and which obtain a signalelectric-charge by receiving light; a column electric-charge transferunit which transfers said signal electric-charge obtained by saidphoto-conductive unit in the direction of said column; and anelectric-charge detection unit which is provided for every plurality ofsaid adjacent columns and which converts said signal electric-chargetransferred by said column electric-charge transfer unit into a pixelsignal; wherein with respect to said plurality of adjacent columns, whensaid signal electric-charge obtained by said photo-conductive unit atthe same position in the direction of said row reaches saidelectric-charge detection unit, a phase of the electric-charge transferis made different.
 2. A solid state image sensor comprising: a pluralityof photo conductive units which are arranged in each direction of therow and the column in the two-dimensional shape and which obtain asignal electric-charge by receiving light; a column electric-chargetransfer unit which transfers said signal electric-charge obtained bysaid photo conductive unit in the direction of said column; anelectric-charge detection unit which is provided for every plurality ofsaid adjacent columns and which converts said signal electric-chargetransferred by said column electric-charge transfer unit into a pixelsignal; and a dummy electric-charge transfer unit arranged between saidcolumn electric-charge transfer unit and said electric-charge detectionunit, in which the number of stages of electric-charge transfer isdifferent with respect to each of said plurality of columns.
 3. Thesolid state image sensor according to claim 2, wherein in theelectric-charge transfer units of said plurality of adjacent columns, anelectrode used for the vertical transfer drive is used in common.
 4. Thesolid state image sensor according to claim 2, wherein saidelectric-charge detection unit is provided for every two said adjacentcolumns.
 5. The solid state image sensor according to claim 4, whereinin said dummy electric-charge transfer unit, the number of stages ofsaid electric-charge transfer is different to the extent that a phase ofthe electric-charge transfer becomes 180 degrees inverted between saidtwo adjacent columns, when said signal electric-charge at the sameposition in the direction of said row is made to reach saidelectric-charge detection unit.
 6. A solid state image sensorcomprising: a plurality of photo conductive units which are arranged ineach direction of the row and the column in the two-dimensional shapeand which obtain a signal electric-charge by receiving light; a columnelectric-charge transfer unit which transfers said signalelectric-charge obtained by said photo conductive unit in the directionof said column; and an electric-charge detection unit provided for everyplurality of said adjacent columns and which converts said signalelectric-charge transferred by said column electric-charge transfer unitinto a pixel signal, wherein an electrode used for driving a verticaltransfer is formed such that a phase of electric-charge transfer whensaid signal electric-charge obtained by said photo-conductive unit atthe same position in the direction of said row reaches saidelectric-charge detection unit is different, when a common verticaltransfer control signal is applied to said plurality of adjacentcolumns.
 7. The solid state image sensor according to claim 1, whereinsaid electric-charge detection unit includes a selective gate, which isshared with said plurality of adjacent columns, for reading out saidsignal electric-charge on the input side of said signal electric-charge.8. The solid state image sensor according to claim 2, wherein saidelectric-charge detection unit includes a selective gate, which isshared with said plurality of adjacent columns, for reading out saidsignal electric-charge on the input side of said signal electric-charge.9. The solid state image sensor according to claim 6, wherein saidelectric-charge detection unit includes a selective gate, which isshared with said plurality of adjacent columns, for reading out saidsignal electric-charge on the input side of said signal electric-charge.10. The solid state image sensor according to claim 1, wherein a wiringto said selective gate is shared with the wiring to said selective gatewith respect to said electric-charge detection units of adjacent others.11. The solid state image sensor according to claim 2, wherein a wiringof said selective gate is shared with the wiring to said selective gatewith respect to said electric-charge detection units of adjacent others.12. The solid state image sensor according to claim 6, wherein a wiringof said selective gate is shared with the wiring to said selective gatewith respect to said electric-charge detection units of adjacent others.13. A solid state image sensor comprising: a plurality ofphoto-conductive units which are arranged in each direction of the rowand the column in the two-dimensional shape and which obtain a signalelectric-charge by receiving light; a column electric-charge transferunit which transfers said signal electric-charge obtained by saidphoto-conductive unit in the direction of said column; and anelectric-charge detection unit which is provided for every two of saidcolumns and which converts said signal electric-charges transferred bysaid column electric-charge transfer unit into a pixel signal, whereinsaid electric-charge detection unit includes a selective gate which isprovided independently for each of said two adjacent columns for readingout said signal electric-charge on the input side of said signalelectric-charge.
 14. The solid state image sensor according to claim 1,wherein each of said electric-charge detection units includes a resetgate in said electric-charge detection unit to be initialized after saidsignal electric-charge is converted into said pixel signal.
 15. Thesolid state image sensor according to claim 2, wherein each of saidelectric-charge detection units includes a reset gate in saidelectric-charge detection unit to be initialized after said signalelectric-charge is converted into said pixel signal.
 16. The solid stateimage sensor according to claim 6, wherein each of said electric-chargedetection units includes a reset gate in said electric-charge detectionunit to be initialized after said signal electric-charge is convertedinto said pixel signal.
 17. The solid state image sensor according toclaim 13, wherein each of said electric-charge detection units includesa reset gate in said electric-charge detection unit to be initializedafter said signal electric-charge is converted into said pixel signal.18. The solid state image sensor according to claim 1, wherein adifferential detection unit which detects the difference between theoutput without said signal electric-charge and the signal level withsaid signal electric-charge, of said pixel signal, is providedsubsequently to said electric-charge detection unit.
 19. The solid stateimage sensor according to claim 2, wherein a differential detection unitwhich detects the difference between the output without said signalelectric-charge and the signal level with said signal electric-charge,of said pixel signal, is provided subsequently to said electric-chargedetection unit.
 20. The solid state image sensor according to claim 6,wherein a differential detection unit which detects the differencebetween the output without said signal electric-charge and the signallevel with said signal electric-charge, of said pixel signal, isprovided subsequently to said electric-charge detection unit.
 21. Thesolid state image sensor according to claim 13, wherein a differentialdetection unit which detects the difference between the output withoutsaid signal electric-charge and the signal level with said signalelectric-charge, of said pixel signal, is provided subsequently to saidelectric-charge detection unit.
 22. The solid state image sensoraccording to claim 1, further comprising: a plurality of saidelectric-charge detection units with respect to said plurality ofadjacent columns in the direction of said column with said plurality ofcolumns as a group, and a horizontal scanning unit subsequent to saidplurality of electric-charge detection units, which sequentially selectsand outputs said pixel signal that is output from each of said pluralityof electric-charge detection units in time series in the direction ofsaid row.
 23. The solid state image sensor according to claim 2 furthercomprising: a plurality of said electric-charge detection units withrespect to said plurality of adjacent columns in the direction of saidcolumn with said plurality of columns as a group, and a horizontalscanning unit subsequent to said plurality of electric-charge detectionunits, which sequentially selects and outputs said pixel signal that isoutput from each of said plurality of electric-charge detection units intime series in the direction of said row.
 24. The solid state imagesensor according to claim 6 further comprising: a plurality of saidelectric-charge detection units with respect to said plurality ofadjacent columns in the direction of said column with said plurality ofcolumns as a group, and a horizontal scanning unit subsequent to saidplurality of electric-charge detection units, which sequentially selectsand outputs said pixel signal that is output from each of said pluralityof electric-charge detection units in time series in the direction ofsaid row.
 25. The solid state image sensor according to claim 13 furthercomprising: a plurality of said electric-charge detection units withrespect to said plurality of adjacent columns in the direction of saidcolumn with said plurality of columns as a group, and a horizontalscanning unit subsequent to said plurality of electric-charge detectionunits, which sequentially selects and outputs said pixel signal that isoutput from each of said plurality of electric-charge detection units intime series in the direction of said row.
 26. A drive method of a solidstate image sensor, in which a pixel signal is obtained from a solidstate image sensor that includes a column electric-charge transfer unitwhich transfers signal electric-charge obtained by photo-conductiveunits arranged in each direction of the row and the column in thetwo-dimensional shape in the direction of said column, and anelectric-charge detection unit which is provided for every plurality ofsaid adjacent columns and which converts said signal electric-chargetransferred by said column electric-charge transfer unit in thedirection of said column into a pixel signal, wherein said solid stateimage sensor is driven such that said pixel signal with respect to eachof said plurality of said adjacent columns is output with a differentphase when said signal electric-charge is transferred in the directionof said columns.
 27. The drive method according to claim 26, whereinsaid column electric-charge transfer unit is driven by six-phase drive.28. The drive method according to claim 26, wherein said electric-chargedetection unit includes on the input side of said signal electric-chargea selective gate for reading out said signal electric-charge, and areset gate for initializing after said signal electric-charge isconverted into said pixel signal, and said reset gate is made to turn onwhen said selective gate is off.
 29. An image pick-up method to obtainan image signal using a solid state image sensor that includes a columnelectric-charge transfer unit which transfers the signal electric-chargeobtained by the photo-conductive units arranged in each direction of therow and the column in the two-dimensional shape in the direction of saidcolumn, and an electric-charge detection unit which is provided forevery plurality of said adjacent columns and which converts said signalelectric-charge transferred by said column electric-charge transfer unitin the direction of said column into a pixel signal, wherein said pixelsignal with respect to each of said plurality of said adjacent columnsis obtained having a different phase in the transfer of said signalelectric-charge in the direction of said columns; the obtained pixelsignal is sequentially selected in time series in the direction of saidrow, so that the image signal with respect to each of said differentphases is obtained; and after that, the image signal sequentiallyaligned in the direction of said row is obtained by rearranging saidpixel signals of said image signal in the direction of said row inaccordance with the order of said plurality of columns.
 30. The drivemethod according to claim 29, wherein said column electric-chargetransfer unit is driven by six-phase drive.
 31. An image pick-up devicecomprising: a solid state image sensor, including: a plurality ofphoto-conductive units which are arranged in each direction of the rowand the column in the two-dimensional shape and which obtain a signalelectric-charge by receiving light, a column electric-charge transferunit which transfers said signal electric-charge obtained by saidphoto-conductive unit in the direction of said column, anelectric-charge detection unit which is provided for every plurality ofsaid columns and which converts said signal electric-charge transferredby said column electric-charge transfer unit into a pixel signal, and adummy electric-charge transfer unit arranged between said columnelectric-charge transfer unit and said electric-charge detection unit,in which the number of stages of electric-charge transfer is differentwith respect to each of said plurality of columns; a horizontal scanningunit which obtains an image signal with respect to each of saiddifferent phases by sequentially selecting in time series in thedirection of said row said pixel signals that are output from said solidstate image sensor with the different phases in the transfer in thedirection of said columns of said signal electric-charges; and a rowadjustment unit which obtains the image signal sequentially aligned inthe direction of said row by rearranging said pixel signals of the imagesignal that are output from said horizontal scanning unit in thedirection of said row in accordance with the order of said plurality ofcolumns.